• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    In one aspect, the invention includes a semiconductor processing method as follows. That is, a) a metal silicide layer 20 is formed on the substrate 12, b) a layer 50 containing silicon, nitrogen and oxygen is deposited on the metal silicide layer 20, and c) a metal silicide layer. Annealed. In another aspect, the invention includes a method of forming a gate stack. a) A polysilicon layer 18 is formed on the substrate 12. b) A metal silicide layer 20 is formed on the polysilicon layer 18. c) An antireflective material layer 50 is deposited over the metal silicide layer 20. d) a silicon nitride layer 24 is formed over the antireflective material layer 50, and e) a photoresist layer 28 is formed over the silicon nitride layer 24. f) The photoresist layer is patterned by photolithography to form a mask layer from the photoresist layer 28. g) a pattern is transferred from the mask layer to the silicon nitride layer 24, the antireflective material layer 50, the metal silicide layer 20, and the polysilicon layer 18, so that the silicon nitride layer, the antireflective material layer, the metal silicide layer, The polysilicon layer is patterned into a gate stacked structure. In another aspect, the invention includes a semiconductor circuit and a gate stack.
    公开号:KR20010073111A
    申请号:KR1020017002811
    申请日:1999-08-31
    公开日:2001-07-31
    发明作者:지핑 인；라비 이에르；토마스알. 글래스；리차드 호슬러；아르다반 니루맨드；린다케이. 좀머빌；거테이에스. 산듀
    申请人:추후제출；미크론 테크놀로지,인코포레이티드；
    IPC主号:
    专利说明:

    Semiconductor process method, semiconductor circuit and gate stack structure {SEMICONDUCTOR PROCESSING METHOD, SEMICONDUCTOR CIRCUITRY, AND GATE STACKS}
    [2] Semiconductor processing methods often involve the process of patterning a material layer to form a transistor gate structure. 1 shows a semiconductor wafer 10 in a preliminary stage of the prior art gate structure patterning process. The semiconductor wafer 10 includes a substrate 12 having a stack 14 of materials. Substrate 12 may include, for example, single crystal silicon that is lightly doped with a p-type dopant. To aid the interpretation of the appended claims, the term "semiconductor substrate" refers to any structure including bulk semiconductor materials, such as but not limited to semiconductor wafers, and semiconductor materials, including but not limited to semiconductor material layers. The term " substrate " means all support structures including, but not limited to, the semiconductor substrates described above.
    [3] The stacked structure 14 includes a gate oxide layer 16, a polysilicon layer 18, a metal silicide layer 20, an oxide layer 22, a nitride layer 24, an antireflective material layer 26, and a photoresist. Layer 28. The gate oxide layer 16 may comprise silicon dioxide, for example, and forms an insulating layer between the polysilicon layer 18 and the substrate 12. Polysilicon layer 18 may comprise, for example, conductive doped polysilicon and will eventually be patterned into the first conducting portion of the transistor gate.
    [4] The silicide layer 20 includes a metal silicide such as tungsten silicide or titanium silicide, and eventually includes a second conductive portion of the transistor gate. Prior to using the silicide layer 20 as a conductive portion of the transistor gate, the silicide is annealed to improve the conductivity and crystal purity of the silicide layer 20. This annealing process may include, for example, a condition of 800-900 degrees Celsius for 30 minutes in a nitrogen (N2) atmosphere.
    [5] When the silicide layer 20 is exposed to gaseous oxygen during the annealing treatment, the silicide layer may be oxidized, which may adversely affect the conductivity of the silicide layer. Thus, an oxide layer 22 is provided over the silicide layer 20 prior to the annealing treatment. The oxide layer 22 may, for example, comprise silicon dioxide. Another purpose of having an oxide layer 22 over the silicide layer 20 is to provide an insulating layer to prevent electrical contact between the silicide layer 20 and another insulating layer formed eventually adjacent to the silicide layer 20. It is to play a role.
    [6] The nitride layer 24 may comprise silicon nitride, for example, and is provided to insulate the conductive layers 18 and 20 from other conductive layers. In this case, the other conductive layers are layers that can be formed eventually adjacent to the layers 18 and 20. Nitride layer 24 is a thick layer (typically hundreds to thousands of angstroms thick), which can create stress in the underlying layer. Thus, another function of the oxide layer 22 is to relieve the stresses generated by the nitride layer 24 in the lower layers 18 and 20.
    [7] The antireflective material layer 26 may include an organic layer formed on the nitride layer 24. Alternatively, the antireflective material layer 26 may be a deposited inorganic antireflective material such as Si x O y N z : H, where x is 0.39-0.65, y is 0.02-0.56, and z is 0.05-0.33. . Indeed, the layer is essentially inorganic, where "essentially inorganic" means that the antireflective material layer may comprise a small amount of carbon (less than 1% by weight). Alternatively, when organic precursors are used, the layer may comprise at least 1% carbon by weight.
    [8] Photoresist layer 28 may comprise a positive or negative photoresist. Photoresist layer 28 is patterned by exposing the layer to light through a masked light source. The mask includes transparent and opaque features that form a pattern to be created in photoresist layer 28. The area of the photoresist layer 28 that is exposed to light is made soluble or insoluble in the solvent. If the exposed area is soluble, a positive phase of the mask is created in the photoresist layer 28, which is called a positive photoresist. In contrast, when the non-radiative region is insoluble in the solvent, a negative phase is produced and the photoresist is called a negative photoresist.
    [9] Difficulties that may arise when exposing the photoresist layer 28 to radiation waves are that radiation waves propagate through the photoresist layer 28 to a layer below the photoresist layer and reflect back through the photoresist layer to It can cause interference with waves propagating through it. The reflected wave may cause other waves and constructive or destructive interference, thereby periodically changing the light intensity in the photoresist layer. This change in light intensity allows the photoresist layer to accommodate a non-uniform distribution of energy throughout its thickness. This non-uniform distribution degrades the accuracy when the masked pattern is transferred to the photoresist layer. An antireflective material 26 is provided to prevent the wave from reflecting back into the photoresist layer 28. Antireflective layer 26 includes a material that absorbs or attenuates radiation, thereby reducing or eliminating the reflection of waves.
    [10] 2 shows the wafer 10 after the photoresist layer 28 is patterned by exposing it to light and a solvent to remove a portion of the photoresist layer 28.
    [11] In FIG. 3, the pattern is transferred from the photoresist layer 28 to the underlying layers 16, 18, 20, 22, 24, 26 to form the patterned stacked structure 30. Such pattern transitions from the mask layer 28 may occur by suitable etching, such as plasma etching with one or more of Cl, HBr, CH 2 F 2 , He, and NF 3 .
    [12] After patterning layers 16, 18, 20, 22, 24, 26, layers 28, 26 are patterned gate stacks comprising layers 16, 18, 20, 22, 24 ( May be removed to leave 30).
    [13] A continuing goal in semiconductor wafer fabrication technology is to reduce the complexity of the process. Such a reduction can be achieved, for example, by reducing the number of process steps or by reducing the number of layers used to form a particular semiconductor structure. Thus, it would be desirable to develop an alternative method of forming a patterned gate stack structure that uses fewer steps or layers than the steps and layers used in the prior art embodiments described in FIGS. 1-3.
    [1] The invention relates to methods of forming and using antireflective materials. The invention also relates to a semiconductor processing method for forming a stacked structure of a material such as a gate stacked structure.
    [17] 1 is a cross-sectional view of a semiconductor wafer at a preliminary stage of an existing process sequence.
    [18] 2 is a diagram of an existing process step of the next sequence of FIG.
    [19] 3 is a diagram of an existing process step of the next sequence of FIG.
    [20] 4 is a cross-sectional view of a semiconductor wafer at an eviction process step in the method of the present invention.
    [21] 5 is a view of the process steps in the following sequence of FIG.
    [22] 6 is a view of the process steps in the next sequence of FIG.
    [23] (Description of symbols in the drawings)
    [24] 10, 10a ... semiconductor wafer 12 ... substrate
    [25] 14, 60 ... laminated structure 16 ... gate oxide layer
    [26] 18 ... polysilicon layer 20 ... metal silicide layer
    [27] 22 ... oxide layer 24 ... nitride layer
    [28] 26 ... antireflective material layer 28 ... photoresist layer
    [29] 50 ... layer containing silicon, oxygen, nitrogen
    [30] 70 ... gate stack
    [14] In one aspect, the invention includes a semiconductor processing method. A metal silicide layer is formed on the substrate. The antireflective material layer is chemical vapor deposited so as to be in direct contact with the metal silicide layer. A photoresist layer is applied over the antireflective material layer and patterned in a photolithographic manner.
    [15] In another aspect, the invention includes a method of forming a gate stack. A polysilicon layer is formed on the substrate. A metal silicide layer is formed on the polysilicon layer. An antireflective material layer is deposited over the metal silicide layer. A silicon nitride layer is formed over the antireflective material layer, and a photoresist layer is formed over the silicon nitride layer. The photoresist layer is patterned by photolithography to form a mask layer from the photoresist layer. The pattern is transferred from the mask layer to the silicon nitride layer, the antireflective material layer, the metal silicide layer, and the polysilicon layer to pattern the silicon nitride layer, the antireflective material layer, the metal silicide layer, and the polysilicon layer into a gate stacked structure.
    [16] In another aspect, the invention includes a gate stack comprising a polysilicon layer over a semiconductor substrate. The gate stacked structure further includes a metal silicide layer on the polysilicon layer and a layer including silicon, oxygen, and nitrogen on the metal silicide layer. In addition, the gate stack includes a silicon nitride layer over the layer comprising silicon, oxygen, and nitrogen.
    [31] Embodiments included in the present invention are described with reference to Figs. 4-6. In describing the embodiments of FIGS. 4-6, reference numerals similar to those used in the description of the prior art of FIGS. 1-3 are used, with differences being indicated by the subscript “a” or other reference numerals.
    [32] In Fig. 4, the semiconductor wafer 10a in the preliminary processing step is shown. Like the wafers 10 of FIGS. 1-3, the wafer 10a includes a substrate 12, a gate oxide layer 16, a polysilicon layer 18, and a silicide layer 20. However, unlike in the prior art described above with reference to FIGS. 1-3, a layer 50 comprising silicon, nitrogen, and oxygen is formed over the silicide layer 20, in the preferred embodiment of the figure directly the silicide layer 20. It is located above. Thus layer 50 replaces oxide layer 22 of the prior art embodiments of FIGS. 1-3.
    [33] It is preferred that the layer 50 be formed by chemical vapor deposition. For example, layer 50 may be formed by CVD using SiH 4 and N 2 O as a precursor in the reactor chamber at 400 degrees Celsius. Such deposition may be performed with or without plasma present in the reaction chamber. Examples of conditions for layer 50 deposition include SiH 4 (preferably 80 sccm) at 40-300 sccm, N 2 O (preferably 80 sccm) at 80-600 sccm, and He (2200 sccm at 1300-2500 sccm). ) In a plasma-enhanced CVD chamber, where the pressure in the chamber is 4-6.5 Torr and the power supplied to the chamber is 50-200 watts (100 watts is preferred).
    [34] Examples of the conditions described above may also include flowing nitrogen gas (N 2 ) into the reactor chamber at a rate of 300 sccm or less (200 sccm is preferred), or ammonia (NH 3 ) at a rate of 100 sccm or less. Can be.
    [35] An example of the composition of layer 50 is Si x N y O z : H, where x is 0.5, y is 0.37, and z is 0.13. The relative values of x, y, z and hydrogen content can be adjusted to alter the absorption characteristics of the deposited material. The thickness of layer 50 is preferably 250-650 angstroms.
    [36] It is preferred to provide a layer 50 over the silicide layer 20 prior to annealing the silicide layer 20. Thus, layer 50 provides the previously described function of oxide layer 22 to protect the silicide layer 20 from exposure of gaseous oxygen when annealing the silicide layer.
    [37] Silicon nitride layer 24 is formed over layer 50 and may be in direct contact with layer 50. As described in the paragraph “Background Art”, silicon nitride layer 24 may stress the underlying layer. Thus, the layer 50 can function as a known silicon dioxide layer 22 to mitigate such stresses so as not to adversely affect the underlying conductive layers 18, 20. The silicon nitride layer 24 may be formed on the layer 50 before and after annealing the silicide layer 20.
    [38] The photoresist layer 28 is formed on the silicon nitride layer 24. Unlike the known embodiments described with reference to FIGS. 1-3, no antireflective material layer is formed between the silicon nitride layer 24 and the photoresist layer 28. Instead, it is preferred to use layer 50 to function as an antireflective material. In particular, the nitride layer 24 is transparent (efficient) to radiation waves used for patterning the photoresist layer 28. Thus, radiation waves that pass through the photoresist layer 28 generally pass through the silicon nitride layer 24 and enter the layer 50. The layer 50 having a chemical structure of nitrogen, oxygen, and silicon is suitably adjusted to dissipate radiation reaching the layer 50 to prevent the reflection of the radiation wave back into the photoresist layer 28. Such chemical structure control can be controlled experimentally using methods known to those of ordinary skill in the art. Another way of describing the adjustment of layers 24 and 50 is that layers 24 and 50 have a thickness (adjust the thickness of one or more of layers 24 and 50) and a formula (adjust the formula of layer 50). Controlled to minimize reflection back to the underlying layer, such as a photoresist layer.
    [39] In FIG. 5, photoresist layer 28 is patterned to form a patterned mask over stacked structure 60 comprising layers 16, 18, 20, 50, 24. In FIG. 6, the pattern is transferred from the photoresist layer 28 to the stack 60 to form a patterned gate stack 70 comprising layers 16, 18, 20, 50, 24. Such pattern transition from photoresist layer 28 may be accomplished by plasma etching using one or more of Cl, HBr, CF 4 , CH 2 F 2 , He, NF 3 , or the like. The photoresist layer 28 may be removed from the gate stacked structure 70. Source and drain regions may then be implanted at locations adjacent the gate stack, and sidewall spacers may be provided on the sidewalls of the gate stack to complete transistor gate construction from the gate stack 70.
    [40] The method of the present invention can reduce the complexity compared to the prior art gate stack formation method described with reference to FIGS. 1-3. In particular, the method of the present invention employs a single layer 50 to 1) protect the silicide layer during annealing, 2) reduce stress from the silicon nitride layer overlying, and 3) photolithography of the photoresist layer overlying. It is possible to achieve various functions described above that mitigate the reflection of light during the process. Thus, the method of the present invention can completely remove one layer (antireflective material layer 26 of FIGS. 1-3) compared to the prior art process described above with reference to FIGS. 1-3. Such layer removal may also eliminate the fabrication steps involved in layer formation and removal. Therefore, the method included in the present invention may be a more efficient semiconductor fabrication process than known methods.
    权利要求:
    Claims (31)
    [1" claim-type="Currently amended] As a semiconductor processing method, the method comprises:
    Forming a metal silicide layer on the substrate,
    Depositing a layer comprising silicon, nitrogen, oxygen on the metal silicide layer, and
    -Annealing the metal silicide layer when a layer comprising silicon, nitrogen, oxygen is placed on the metal silicide layer.
    [2" claim-type="Currently amended] The layer of claim 1, wherein the layer comprising silicon, nitrogen, oxygen comprises Si x N y O z : H wherein x is 0.39-0.65, y is 0.02-0.56, z is in the range of 0.05-0.33. Characterized in that the method.
    [3" claim-type="Currently amended] 3. The method of claim 2, further comprising forming a silicon nitride layer over the layer comprising silicon, nitrogen, oxygen, hydrogen.
    [4" claim-type="Currently amended] 3. The method of claim 2, further comprising forming a silicon nitride layer over the layer comprising silicon, nitrogen, oxygen, hydrogen prior to the annealing treatment.
    [5" claim-type="Currently amended] The method of claim 1, wherein the depositing step comprises chemical vapor deposition.
    [6" claim-type="Currently amended] 2. The method of claim 1, further comprising forming a silicon nitride layer over the layer comprising silicon, nitrogen, and oxygen.
    [7" claim-type="Currently amended] The method of claim 1, further comprising forming a silicon nitride layer over the layer comprising silicon, nitrogen, oxygen prior to the annealing treatment.
    [8" claim-type="Currently amended] As a semiconductor processing method, the method comprises:
    Forming a metal silicide layer on the substrate,
    Depositing a layer comprising silicon, nitrogen, oxygen on the metal silicide layer, and
    -Forming a silicon nitride layer over the layer comprising silicon, nitrogen, oxygen.
    [9" claim-type="Currently amended] 9. The layer of claim 8, wherein the layer comprising silicon, nitrogen, oxygen comprises Si x N y O z : H, wherein x is 0.39-0.65, y is 0.02-0.56, z is in the range of 0.05-0.33. Characterized in that the method.
    [10" claim-type="Currently amended] 9. The method of claim 8, wherein said depositing comprises chemical vapor deposition.
    [11" claim-type="Currently amended] As a semiconductor processing method, the method comprises:
    Forming a metal silicide layer on the substrate,
    Chemical vapor deposition of an antireflective material layer in direct contact with the metal silicide layer;
    Forming a photoresist layer over the antireflective material layer, and
    -Patterning the photoresist layer in a photolithographic manner.
    [12" claim-type="Currently amended] The method of claim 11, wherein the antireflective material layer deposited comprises silicon, nitrogen, oxygen.
    [13" claim-type="Currently amended] 12. The method of claim 11, wherein the antireflective material layer deposited comprises silicon, nitrogen, oxygen, hydrogen.
    [14" claim-type="Currently amended] 12. The method of claim 11, further comprising forming a silicon nitride layer over the layer of antireflective material to be deposited, wherein a photoresist layer is formed over the silicon nitride layer.
    [15" claim-type="Currently amended] A method of forming a gate stacked structure, the method comprising:
    Forming a polysilicon layer on the substrate,
    Forming a metal silicide layer on the polysilicon layer,
    Depositing an antireflective material layer on the metal silicide layer,
    Forming a silicon nitride layer on the antireflective material layer,
    Forming a photoresist layer on the silicon nitride layer,
    Patterning the photoresist layer in a photolithographic manner to form a patterned mask layer from the photoresist layer, and
    To pattern the silicon nitride layer, antireflective material layer, metal silicide layer, and polysilicon layer into a gate stacked structure, patterning is performed from the patterned mask layer to the silicon nitride layer, antireflective material layer, metal silicide layer, and polysilicon layer. Transition, the method comprising the above steps.
    [16" claim-type="Currently amended] 16. The method of claim 15, further comprising annealing the metal silicide layer when the antireflective material layer is on the metal silicide layer.
    [17" claim-type="Currently amended] The method of claim 15, wherein said depositing comprises chemical vapor deposition.
    [18" claim-type="Currently amended] The method of claim 15, wherein the layer of antireflective material deposited comprises silicon, nitrogen, oxygen, hydrogen.
    [19" claim-type="Currently amended] 16. The method of claim 15, wherein the layer of antireflective material to be deposited comprises silicon, nitrogen, oxygen.
    [20" claim-type="Currently amended] 20. The method of claim 19, wherein the layer comprising silicon, nitrogen, and oxygen is in direct contact with the metal silicide layer.
    [21" claim-type="Currently amended] 20. The method of claim 19, wherein the silicon nitride layer is in direct contact with the layer comprising silicon, nitrogen, and oxygen.
    [22" claim-type="Currently amended] 20. The method of claim 19, wherein the silicon nitride layer is in direct contact with the layer comprising silicon, nitrogen, and oxygen, and the layer comprising silicon, nitrogen, and oxygen is in direct contact with the metal silicide layer.
    [23" claim-type="Currently amended] A metal silicide layer on the semiconductor substrate, and
    A circuit circuit comprising an intrinsic inorganic layer comprising silicon, nitrogen and oxygen in direct contact with the metal silicide layer.
    [24" claim-type="Currently amended] 24. The circuit of claim 23, wherein the layer comprising silicon, nitrogen, and oxygen is located above the metal silicide layer, and wherein the circuit further comprises a silicon nitride layer over the layer comprising silicon, nitrogen, and oxygen.
    [25" claim-type="Currently amended] 24. The method of claim 23, wherein the layer comprising silicon, nitrogen, and oxygen is formed over the metal silicide layer, and the circuit further comprises a silicon nitride layer in direct contact over the layer comprising silicon, nitrogen, and oxygen. Circuit.
    [26" claim-type="Currently amended] The layer of claim 23 wherein the layer comprising silicon, nitrogen, oxygen comprises Si x N y O z : H, wherein x is 0.39-0.65, y is 0.02-0.56, z is in the range of 0.05-0.33. Circuit, characterized in that.
    [27" claim-type="Currently amended] A polysilicon layer on a semiconductor substrate,
    A metal silicide layer on the polysilicon layer,
    A layer comprising silicon, nitrogen, oxygen on the metal silicide layer, and
    A gate stack comprising a silicon nitride layer over the layer comprising silicon, nitrogen and oxygen.
    [28" claim-type="Currently amended] The layer of claim 27, wherein the layer comprising silicon, nitrogen, oxygen comprises Si x N y O z , wherein x is 0.39-0.65, y is 0.02-0.56, z is in the range of 0.05-0.33. Circuit.
    [29" claim-type="Currently amended] 28. The circuit of claim 27 wherein the layer comprising silicon, nitrogen, and oxygen is in direct contact with the metal silicide layer.
    [30" claim-type="Currently amended] 28. The circuit of claim 27, wherein the silicon nitride layer is in direct contact with the layer comprising silicon, nitrogen, and oxygen.
    [31" claim-type="Currently amended] 28. The circuit of claim 27, wherein the silicon nitride layer is in direct contact with the layer comprising silicon, nitrogen, and oxygen, and the layer comprising silicon, nitrogen, and oxygen is in direct contact with the metal silicide layer.
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    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    1998-09-03|Priority to US09/146,842
    1998-09-03|Priority to US09/146,842
    1999-08-31|Application filed by 추후제출, 미크론 테크놀로지,인코포레이티드
    2001-07-31|Publication of KR20010073111A
    2004-06-07|Application granted
    2004-06-07|Publication of KR100434560B1
    优先权:
    申请号 | 申请日 | 专利标题
    US09/146,842|US6281100B1|1998-09-03|1998-09-03|Semiconductor processing methods|
    US09/146,842|1998-09-03|
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